Electronic enthusiast network Core Tip: Awarded NIOS® II Embedded Processor C Language to Hardware (C2H) Acceleration Compiler Transforms the Hardware Accelerator in FPGA to the FPGA, which requires higher time requirements.
Features:
(1) ANSI / ISO C code button acceleration
(2) Tight intensity of software design processes
(3) Direct connection of hardware accelerator and CPU memory mapping
(4) Seamless support pointers and arrays
(5) Efficient memory processing delay predictive dispatch and pipeline
Reduce power consumption by increasing hardware
System design experience has always been considered to increase hardware to increase power consumption. However, careful use of hardware accelerator breaks this experience: increasing hardware will reduce power consumption. By analyzing the algorithm, the appropriate accelerator is implemented in programmable logic, not only enhances the design performance of the embedded computing system, but also reduces power consumption.
Considering such an example, the embedded designer wants the processor to execute the program at an 80 MHz, uninstalling the algorithm of the large computation amount into a lower clock frequency. As shown in Table 1, in the actual test, the embedded processor runs the application code at 80 MHz, and the 5 hardware accelerator runs at 1 MHz, and the system performance has increased by 6 times, and the system power consumption is reduced by 55%.
Largely improve the performance of embedded software
For software engineers that need to improve embedded application performance, hardware acceleration is the most important tool. The hardware accelerator can give full play to the advantages of the FPGA parallel processing structure, compared to the general CPU, completing more computing per clock cycle, and performance has improved several orders. Please refer to Table 2 for the performance and area results of several common embedded algorithms.
Table 1 Note: System resources improve the logical unit equivalence cost of the in-chip resources, such as multipliers and memory, showing the cost after adding accelerator and buffer. These data indicate that the NIOS II C2H compiler can greatly improve system performance with minimal cost and resource.
Familiar software design process
So far, it has always been manually uninstalled to the hardware accelerator, only those developers with tools, experience and time can use this technology to establish, test register transfer grade (RTL) modules, and integrated into the processor system . The NIOS II C2H compiler automatically establishes and integrates hardware accelerator, and the development time is shortened by a few minutes a few minutes.
If you have previously used Eclipse-based NIOS II Integrated Development Environment (IDE), it will be very simple to use Nios II C2H. The work you need to do is:
Analyze the software code to determine the function of the performance bottleneck.
Highlight the desired function in the NIOS II IDE, right-click Acceleration.
View the detailed C2H compiler report file to determine the simple C code optimization.
Optimize and iterate until the desired performance is reached.
Quickly reach the performance requirements of your application, and launch products in advance.
The NIOS II C2H compiler allows you to quickly efficiently optimize your application algorithm in design space, which is only for software implementation. You need to do just right click on the speed.
Ordering Information
You can now order the NIOS II C2H compiler. Please refer to the price and ordering information of Table 2. You can download and free to evaluate the NIOS II Embedded Design Set (EDS). Please contact your local Altera sales representative for more information. Technology area
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